Image_Processing_By_Verilog
موضوع
Invert / Threshold / Brightness
بررسی
طبیعتا تا به حال پردازش تصویر در خیلی از موارد مثل MATLAB , openCV , python , raspberry PI و یا حتی در آردویینو دیده اید .
در این حالات شما با 10 خط شاید بتوانید میزان روشنایی و یا آستانه گذاری را انجام دهید ولی در fpga همچین خبری نیست و برای سه ویرایش ساده در تصویر شما باید نزدیک 1500 خط کد بنویسید .
در fpga کتابخانه و یا دستوری برای فراخوانی نبوده ، نیست و نخواهد بود ، شما باید خودتان مراحل پردازش روی تک تک پیکسل هارا انجام بدهید و این کارها در زمان های خاص انجام میشود و باید کلاک درست و معقولی را انتخاب کنید .
در این آموزش سعی شده که بر روی تصویر زیر یک سری تغییرات را اعمال کنیم .
این تصویر دارای مشخصات زیر است :
format : bmp
width : 768
height : 512
bit depth : 24
با پردازش هایی که ما انجام میدهیم خروجی به صورت زیر ظاهر میشود .
1) کاهش روشنایی
در این حالت ما مستقیما با مقدار سبز و قرمز و آبی هر پیکسل کار داریم و برای کاهش روشنایی از مقادیر rgb هر پیکسل مقدار مورد نظر را کم میکنیم اگر کوچکتر از صفر شد که صفر را قرار میدهیم ولی اگر از صفر کمتر نشد مقادیرش همان مقادیر حساب شده اش میشود .
2) افزایش روشنایی :
در این حالت ما مستقیما با مقدار سبز و قرمز و آبی هر پیکسل کار داریم و برای افزایش روشنایی به مقادیر rgb هر پیکسل مقدار مورد نظر را اضافه میکنیم اگر بزرگتر از 255 شد که 255 را قرار میدهیم ولی اگر از 255 بیشتر نشد مقادیرش همان مقادیر حساب شده اش میشود .
3) Invert :
در این عملیات قرار است ما کار معکوس سازی در حالت gray scale را انجام دهیم به این صورت که مقدار 255 را از میانگین هر سه رنگ قرمز و سبز و آبی در هر پیکسل کم میکنیم و مقدار مورد نظر همان مقادیر معکوس شده هر پیکسل است .
4) آستانه ( Threshold ) :
در این عملیات یک مقادیری را به عنوان حد آستانه تعیین میکنیم و اگر میانگین سبز و آبی و قرمز هر پیکسل از آن حد آستانه بیشتر شود رنگ مقادیر 1 را میگیرد و اگر کمتر شود رنگ مقادیر 0 را میگیرد .
کد پروژه ( تعریف نوع فعالیت )
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/*************************** **********************************************/ /*************************** Definition file ******************************/ /*************************** **********************************************/ // By octacore.ir `define INPUTFILENAME "Qazvin_shazde_Hossein.hex" // Input file name `define OUTPUTFILENAME "Qazvin_shazde_Hossein_out.bmp" // Output file name // Choose the operation of code by delete // in the beginning of the selected line `define BRIGHTNESS_OPERATION //`define INVERT_OPERATION //`define THRESHOLD_OPERATION |
کد پروژه ( خواندن تصویر )
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// By octacore.ir /******************************************************************************/ /****************** Module for reading and processing image **************/ /******************************************************************************/ `include "parameter.v" // Include definition file module image_read # ( parameter WIDTH = 768 , // Image width HEIGHT = 512 , // Image height INFILE = "Qazvin_shazde_Hossein.hex" , // image file START_UP_DELAY = 100 , // Delay during start up time HSYNC_DELAY = 160 , // Delay between HSYNC pulses VALUE = 100 , // value for Brightness operation THRESHOLD = 90 , // Threshold value for Threshold operation SIGN = 1 // Sign value using for brightness operation // SIGN = 0: Brightness subtraction // SIGN = 1: Brightness addition ) ( input HCLK , // clock input HRESETn , // Reset (active low) output VSYNC , // Vertical synchronous pulse // This signal is often a way to indicate that one entire image is transmitted. // Just create and is not used, will be used once a video or many images are transmitted. output reg HSYNC , // Horizontal synchronous pulse // An HSYNC indicates that one line of the image is transmitted. // Used to be a horizontal synchronous signals for writing bmp file. output reg [ 7 : 0 ] DATA_R0 , // 8 bit Red data (even) output reg [ 7 : 0 ] DATA_G0 , // 8 bit Green data (even) output reg [ 7 : 0 ] DATA_B0 , // 8 bit Blue data (even) output reg [ 7 : 0 ] DATA_R1 , // 8 bit Red data (odd) output reg [ 7 : 0 ] DATA_G1 , // 8 bit Green data (odd) output reg [ 7 : 0 ] DATA_B1 , // 8 bit Blue data (odd) // Process and transmit 2 pixels in parallel to make the process faster, you can modify to transmit 1 pixels or more if needed output ctrl_done // Done flag ) ; //------------------------------------------------- // Internal Signals //------------------------------------------------- parameter sizeOfWidth = 8 ; // data width parameter sizeOfLengthReal = 1179648 ; // image data : 1179648 bytes: 512 * 768 *3 // local parameters for FSM localparam ST_IDLE = 2'b00 , // idle state ST_VSYNC = 2'b01 , // state for creating vsync ST_HSYNC = 2'b10 , // state for creating hsync ST_DATA = 2'b11 ; // state for data processing reg [ 1 : 0 ] cstate , // current state nstate ; // next state reg start ; // start signal: trigger Finite state machine beginning to operate reg HRESETn_d ; // delayed reset signal: use to create start signal reg ctrl_vsync_run ; // control signal for vsync counter reg [ 8 : 0 ] ctrl_vsync_cnt ; // counter for vsync reg ctrl_hsync_run ; // control signal for hsync counter reg [ 8 : 0 ] ctrl_hsync_cnt ; // counter for hsync reg ctrl_data_run ; // control signal for data processing reg [ 31 : 0 ] in_memory [ 0 : sizeOfLengthReal / 4 ] ; // memory to store 32-bit data image reg [ 7 : 0 ] total_memory [ 0 : sizeOfLengthReal -1 ] ; // memory to store 8-bit data image // temporary memory to save image data : size will be WIDTH*HEIGHT*3 integer temp_BMP [ 0 : WIDTH * HEIGHT * 3 - 1 ] ; integer org_R [ 0 : WIDTH * HEIGHT - 1 ] ; // temporary storage for R component integer org_G [ 0 : WIDTH * HEIGHT - 1 ] ; // temporary storage for G component integer org_B [ 0 : WIDTH * HEIGHT - 1 ] ; // temporary storage for B component // counting variables integer i , j ; // temporary signals for calculation: details in the paper. integer tempR0 , tempR1 , tempG0 , tempG1 , tempB0 , tempB1 ; // temporary variables in contrast and brightness operation integer value , value1 , value2 , value4 ; // temporary variables in invert and threshold operation reg [ 9 : 0 ] row ; // row index of the image reg [ 10 : 0 ] col ; // column index of the image reg [ 18 : 0 ] data_count ; // data counting for entire pixels of the image //-------------------------------------------------// // -------- Reading data from input file ----------// //-------------------------------------------------// initial begin $readmemh ( INFILE , total_memory , 0 , sizeOfLengthReal - 1 ) ; // read file from INFILE end // use 3 intermediate signals RGB to save image data always @ ( start ) begin if ( start == 1'b1 ) begin for ( i = 0 ; i < WIDTH * HEIGHT * 3 ; i = i + 1 ) begin temp_BMP [ i ] = total_memory [ i + 0 ] [ 7 : 0 ] ; end for ( i = 0 ; i < HEIGHT ; i = i + 1 ) begin for ( j = 0 ; j < WIDTH ; j = j + 1 ) begin org_R [ WIDTH * i + j ] = temp_BMP [ WIDTH * 3 * ( HEIGHT - i - 1 ) + 3 * j + 0 ] ; // save Red component org_G [ WIDTH * i + j ] = temp_BMP [ WIDTH * 3 * ( HEIGHT - i - 1 ) + 3 * j + 1 ] ; // save Green component org_B [ WIDTH * i + j ] = temp_BMP [ WIDTH * 3 * ( HEIGHT - i - 1 ) + 3 * j + 2 ] ; // save Blue component end end end end //----------------------------------------------------// // ---Begin to read image file once reset was high ---// // ---by creating a starting pulse (start)------------// //----------------------------------------------------// always @ ( posedge HCLK , negedge HRESETn ) begin if( HRESETn == 0 ) begin start <= 0 ; HRESETn_d <= 0 ; end else begin // ______ HRESETn_d <= HRESETn ; // | | if ( HRESETn == 1'b1 && HRESETn_d == 1'b0 ) // __0___| 1 |___0____ : starting pulse start <= 1'b1 ; else start <= 1'b0 ; end end //-----------------------------------------------------------------------------------------------// // Finite state machine for reading RGB888 data from memory and creating hsync and vsync pulses --// //-----------------------------------------------------------------------------------------------// always @ ( posedge HCLK , negedge HRESETn ) begin if( HRESETn == 0 ) begin cstate <= ST_IDLE ; end else begin cstate <= nstate ; // update next state end end //-----------------------------------------// //--------- State Transition --------------// //-----------------------------------------// // IDLE . VSYNC . HSYNC . DATA always @ ( * ) begin case ( cstate ) ST_IDLE : nstate = ( start == 1 ) ? ST_VSYNC : ST_IDLE ; ST_VSYNC: nstate = ( ctrl_vsync_cnt == START_UP_DELAY ) ? ST_HSYNC : ST_VSYNC ; ST_HSYNC: nstate = ( ctrl_hsync_cnt == HSYNC_DELAY ) ? ST_DATA : ST_HSYNC ; ST_DATA: nstate = ( ctrl_done == 1 ) ? ST_IDLE : ( col == WIDTH - 2 ) ? ST_HSYNC : ST_DATA ; endcase end // ------------------------------------------------------------------- // // --- counting for time period of vsync, hsync, data processing ---- // // ------------------------------------------------------------------- // always @ ( * ) begin ctrl_vsync_run = 0 ; ctrl_hsync_run = 0 ; ctrl_data_run = 0 ; case ( cstate ) ST_VSYNC: ctrl_vsync_run = 1 ; // trigger counting for vsync ST_HSYNC: ctrl_hsync_run = 1 ; // trigger counting for hsync ST_DATA: ctrl_data_run = 1 ; // trigger counting for data processing endcase end // counters for vsync, hsync always @ ( posedge HCLK , negedge HRESETn ) begin if( HRESETn == 0 ) begin ctrl_vsync_cnt <= 0 ; ctrl_hsync_cnt <= 0 ; end else begin if ( ctrl_vsync_run == 1 ) ctrl_vsync_cnt <= ctrl_vsync_cnt + 1 ; // counting for vsync else ctrl_vsync_cnt <= 0 ; if ( ctrl_hsync_run == 1 ) ctrl_hsync_cnt <= ctrl_hsync_cnt + 1 ; // counting for hsync else ctrl_hsync_cnt <= 0 ; end end // counting column and row index for reading memory always @ ( posedge HCLK , negedge HRESETn ) begin if ( HRESETn == 0 ) begin row <= 0 ; col <= 0 ; end else begin if ( ctrl_data_run ) begin if ( col == WIDTH - 2 ) begin row <= row + 1 ; end if ( col == WIDTH - 2 ) col <= 0 ; else col <= col + 2 ; // reading 2 pixels in parallel end end end //-------------------------------------------------// //----------------Data counting---------- ---------// //-------------------------------------------------// always @ ( posedge HCLK , negedge HRESETn ) begin if( HRESETn == 0 ) begin data_count <= 0 ; end else begin if ( ctrl_data_run ) data_count <= data_count + 1 ; end end assign VSYNC = ctrl_vsync_run ; assign ctrl_done = ( data_count == 196607 ) ? 1'b1 : 1'b0 ; // done flag //-------------------------------------------------// //------------- Image processing ---------------// //-------------------------------------------------// always @ ( * ) begin HSYNC = 1'b0 ; DATA_R0 = 0 ; DATA_G0 = 0 ; DATA_B0 = 0 ; DATA_R1 = 0 ; DATA_G1 = 0 ; DATA_B1 = 0 ; if ( ctrl_data_run ) begin HSYNC = 1'b1 ; `ifdef BRIGHTNESS_OPERATION /**************************************/ /* BRIGHTNESS ADDITION OPERATION */ /**************************************/ if ( SIGN == 1 ) begin // R0 tempR0 = org_R[WIDTH * row + col ] + VALUE ; if ( tempR0 > 255 ) DATA_R0 = 255 ; else DATA_R0 = org_R [ WIDTH * row + col ] + VALUE ; // R1 tempR1 = org_R[ WIDTH * row + col+1 ] + VALUE ; if ( tempR1 > 255 ) DATA_R1 = 255 ; else DATA_R1 = org_R [ WIDTH * row + col + 1 ] + VALUE ; // G0 tempG0 = org_G [ WIDTH * row + col ] + VALUE ; if ( tempG0 > 255 ) DATA_G0 = 255 ; else DATA_G0 = org_G [ WIDTH * row + col ] + VALUE ; tempG1 = org_G [ WIDTH * row + col + 1 ] + VALUE ; if ( tempG1 > 255 ) DATA_G1 = 255 ; else DATA_G1 = org_G [ WIDTH * row + col + 1 ] + VALUE ; // B tempB0 = org_B [ WIDTH * row + col ] + VALUE ; if ( tempB0 > 255 ) DATA_B0 = 255 ; else DATA_B0 = org_B [ WIDTH * row + col ] + VALUE ; tempB1 = org_B [ WIDTH * row + col + 1 ] + VALUE ; if ( tempB1 > 255 ) DATA_B1 = 255 ; else DATA_B1 = org_B [ WIDTH * row + col + 1 ] + VALUE ; end else begin /**************************************/ /* BRIGHTNESS SUBTRACTION OPERATION */ /**************************************/ // R0 tempR0 = org_R [ WIDTH * row + col ] - VALUE ; if ( tempR0 < 0 ) DATA_R0 = 0 ; else DATA_R0 = org_R [ WIDTH * row + col ] - VALUE ; // R1 tempR1 = org_R [ WIDTH * row + col + 1 ] - VALUE ; if ( tempR1 < 0 ) DATA_R1 = 0 ; else DATA_R1 = org_R [ WIDTH * row + col + 1 ] - VALUE ; // G0 tempG0 = org_G [ WIDTH * row + col ] - VALUE ; if ( tempG0 < 0 ) DATA_G0 = 0 ; else DATA_G0 = org_G [ WIDTH * row + col ] - VALUE ; tempG1 = org_G [ WIDTH * row + col + 1 ] - VALUE ; if ( tempG1 < 0 ) DATA_G1 = 0 ; else DATA_G1 = org_G [ WIDTH * row + col + 1 ] - VALUE ; // B tempB0 = org_B [ WIDTH * row + col ] - VALUE ; if ( tempB0 < 0 ) DATA_B0 = 0 ; else DATA_B0 = org_B [ WIDTH * row + col ] - VALUE ; tempB1 = org_B [ WIDTH * row + col + 1 ] - VALUE ; if ( tempB1 < 0 ) DATA_B1 = 0 ; else DATA_B1 = org_B [ WIDTH * row + col + 1 ] - VALUE ; end `endif /**************************************/ /* INVERT_OPERATION */ /**************************************/ `ifdef INVERT_OPERATION value2 = ( org_B [ WIDTH * row + col ] + org_R [ WIDTH * row + col ] + org_G [ WIDTH * row + col ] ) / 3 ; DATA_R0 = 255 - value2 ; DATA_G0 = 255 - value2 ; DATA_B0 = 255 - value2 ; value4 = ( org_B [ WIDTH * row + col + 1 ] + org_R [ WIDTH * row + col + 1 ] + org_G [ WIDTH * row + col + 1 ] ) / 3 ; DATA_R1 = 255 - value4 ; DATA_G1 = 255 - value4 ; DATA_B1 = 255 - value4 ; `endif /**************************************/ /********THRESHOLD OPERATION *********/ /**************************************/ `ifdef THRESHOLD_OPERATION value = ( org_R [ WIDTH * row + col ] + org_G [ WIDTH * row + col ] + org_B [ WIDTH * row + col ] ) / 3 ; if ( value > THRESHOLD ) begin DATA_R0 = 255 ; DATA_G0 = 255 ; DATA_B0 = 255 ; end else begin DATA_R0 = 0 ; DATA_G0 = 0 ; DATA_B0 = 0 ; end value1 = ( org_R [ WIDTH * row + col + 1 ] + org_G [ WIDTH * row + col + 1 ] + org_B [ WIDTH * row + col + 1 ] ) / 3 ; if ( value1 > THRESHOLD ) begin DATA_R1 = 255 ; DATA_G1 = 255 ; DATA_B1 = 255 ; end else begin DATA_R1 = 0 ; DATA_G1 = 0 ; DATA_B1 = 0 ; end `endif end end endmodule |
کد پروژه ( نوشتن تصویر خروجی )
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/******************************************************************************/ /****************** Module for writing .bmp image *************/ /******************************************************************************/ module image_write # ( parameter WIDTH = 768 , // Image width HEIGHT = 512 , // Image height INFILE = "Qazvin_shazde_Hossein_out.bmp" , // Output image BMP_HEADER_NUM = 54 // Header for bmp image ) ( input HCLK , // Clock input HRESETn , // Reset active low input hsync , // Hsync pulse input [ 7 : 0 ] DATA_WRITE_R0 , // Red 8-bit data (odd) input [ 7 : 0 ] DATA_WRITE_G0 , // Green 8-bit data (odd) input [ 7 : 0 ] DATA_WRITE_B0 , // Blue 8-bit data (odd) input [ 7 : 0 ] DATA_WRITE_R1 , // Red 8-bit data (even) input [ 7 : 0 ] DATA_WRITE_G1 , // Green 8-bit data (even) input [ 7 : 0 ] DATA_WRITE_B1 , // Blue 8-bit data (even) output reg Write_Done ) ; integer BMP_header [ 0 : BMP_HEADER_NUM - 1 ] ; // BMP header reg [ 7 : 0 ] out_BMP [ 0 : WIDTH * HEIGHT * 3 - 1 ] ; // Temporary memory for image reg [ 18 : 0 ] data_count ; // Counting data wire done ; // done flag // counting variables integer i ; integer k , l , m ; integer fd ; //----------------------------------------------------------// //-------Header data for bmp image--------------------------// //----------------------------------------------------------// // Windows BMP files begin with a 54-byte header: // Check the website to see the value of this header: http://www.fastgraph.com/help/bmp_header_format.html initial begin BMP_header [ 0 ] = 66 ; BMP_header [ 28 ] = 24 ; BMP_header [ 1 ] = 77 ; BMP_header [ 29 ] = 0 ; BMP_header [ 2 ] = 54 ; BMP_header [ 30 ] = 0 ; BMP_header [ 3 ] = 0 ; BMP_header [ 31 ] = 0 ; BMP_header [ 4 ] = 18 ; BMP_header [ 32 ] = 0 ; BMP_header [ 5 ] = 0 ; BMP_header [ 33 ] = 0 ; BMP_header [ 6 ] = 0 ; BMP_header [ 34 ] = 0 ; BMP_header [ 7 ] = 0 ; BMP_header [ 35 ] = 0 ; BMP_header [ 8 ] = 0 ; BMP_header [ 36 ] = 0 ; BMP_header [ 9 ] = 0 ; BMP_header [ 37 ] = 0 ; BMP_header [ 10 ] = 54 ; BMP_header [ 38 ] = 0 ; BMP_header [ 11 ] = 0 ; BMP_header [ 39 ] = 0 ; BMP_header [ 12 ] = 0 ; BMP_header [ 40 ] = 0 ; BMP_header [ 13 ] = 0 ; BMP_header [ 41 ] = 0 ; BMP_header [ 14 ] = 40 ; BMP_header [ 42 ] = 0 ; BMP_header [ 15 ] = 0 ; BMP_header [ 43 ] = 0 ; BMP_header [ 16 ] = 0 ; BMP_header [ 44 ] = 0 ; BMP_header [ 17 ] = 0 ; BMP_header [ 45 ] = 0 ; BMP_header [ 18 ] = 0 ; BMP_header [ 46 ] = 0 ; BMP_header [ 19 ] = 3 ; BMP_header [ 47 ] = 0 ; BMP_header [ 20 ] = 0 ; BMP_header [ 48 ] = 0 ; BMP_header [ 21 ] = 0 ; BMP_header [ 49 ] = 0 ; BMP_header [ 22 ] = 0 ; BMP_header [ 50 ] = 0 ; BMP_header [ 23 ] = 2 ; BMP_header [ 51 ] = 0 ; BMP_header [ 24 ] = 0 ; BMP_header [ 52 ] = 0 ; BMP_header [ 25 ] = 0 ; BMP_header [ 53 ] = 0 ; BMP_header [ 26 ] = 1 ; BMP_header [ 27 ] = 0 ; end // row and column counting for temporary memory of image always @ ( posedge HCLK , negedge HRESETn ) begin if ( HRESETn == 0 ) begin l <= 0 ; m <= 0 ; end else begin if ( hsync ) begin if ( m == WIDTH / 2 - 1 ) begin m <= 0 ; l <= l + 1 ; // count to obtain row index of the out_BMP temporary memory to save image data end else begin m <= m + 1 ; // count to obtain column index of the out_BMP temporary memory to save image data end end end end // Writing RGB888 even and odd data to the temp memory always @ ( posedge HCLK , negedge HRESETn ) begin if ( HRESETn == 0 ) begin for ( k = 0 ; k < WIDTH * HEIGHT * 3 ; k = k + 1 ) begin out_BMP [ k ] <= 0 ; end end else begin if ( hsync ) begin out_BMP [ WIDTH * 3 * ( HEIGHT - l - 1 ) + 6 * m + 2 ] <= DATA_WRITE_R0 ; out_BMP [ WIDTH * 3 * ( HEIGHT - l - 1 ) + 6 * m + 1 ] <= DATA_WRITE_G0 ; out_BMP [ WIDTH * 3 * ( HEIGHT - l - 1 ) + 6 * m ] <= DATA_WRITE_B0 ; out_BMP [ WIDTH * 3 * ( HEIGHT - l - 1 ) + 6 * m + 5 ] <= DATA_WRITE_R1 ; out_BMP [ WIDTH * 3 * ( HEIGHT - l - 1 ) + 6 * m + 4 ] <= DATA_WRITE_G1 ; out_BMP [ WIDTH * 3 * ( HEIGHT - l - 1 ) + 6 * m + 3 ] <= DATA_WRITE_B1 ; end end end // data counting always @ ( posedge HCLK , negedge HRESETn ) begin if ( HRESETn == 0 ) begin data_count <= 0 ; end else begin if ( hsync ) data_count <= data_count + 1 ; // pixels counting for create done flag end end assign done = ( data_count == 196607 ) ? 1'b1 : 1'b0 ; // done flag once all pixels were processed always @ ( posedge HCLK , negedge HRESETn ) begin if ( HRESETn == 0 ) begin Write_Done <= 0 ; end else begin Write_Done <= done ; end end //---------------------------------------------------------// //--------------Write .bmp file ----------------------// //----------------------------------------------------------// initial begin fd = $fopen ( INFILE , "wb+" ) ; end always @ ( Write_Done ) begin // once the processing was done, bmp image will be created if ( Write_Done == 1'b1 ) begin for ( i = 0 ; i < BMP_HEADER_NUM ; i = i + 1 ) begin $fwrite ( fd , "%c" , BMP_header [ i ] [ 7 : 0 ] ) ; // write the header end for ( i = 0 ; i < WIDTH * HEIGHT * 3 ; i = i + 6 ) begin // write R0B0G0 and R1B1G1 (6 bytes) in a loop $fwrite ( fd , "%c" , out_BMP [ i ] [ 7 : 0 ] ) ; $fwrite ( fd , "%c" , out_BMP [ i + 1 ] [ 7 : 0 ] ) ; $fwrite ( fd , "%c" , out_BMP [ i + 2 ] [ 7 : 0 ] ) ; $fwrite ( fd , "%c" , out_BMP [ i + 3 ] [ 7 : 0 ] ) ; $fwrite ( fd , "%c" , out_BMP [ i + 4 ] [ 7 : 0 ] ) ; $fwrite ( fd , "%c" , out_BMP [ i + 5 ] [ 7 : 0 ] ) ; end end end endmodule |
کد شبیه سازی
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`timescale 1ns/1ps /**************************************************************************/ /******************** Testbench for simulation ****************************/ /**************************************************************************/ // By octacore.ir `include "parameter.v" // include definition file module tb_simulation ; //------------------------------------------------- // Internal Signals //------------------------------------------------- reg HCLK , HRESETn ; wire vsync ; wire hsync ; wire [ 7 : 0 ] data_R0 ; wire [ 7 : 0 ] data_G0 ; wire [ 7 : 0 ] data_B0 ; wire [ 7 : 0 ] data_R1 ; wire [ 7 : 0 ] data_G1 ; wire [ 7 : 0 ] data_B1 ; wire enc_done ; //------------------------------------------------- // Components //------------------------------------------------- image_read # ( .INFILE ( `INPUTFILENAME ) ) u_image_read ( .HCLK ( HCLK ) , .HRESETn ( HRESETn ) , .VSYNC ( vsync ) , .HSYNC ( hsync ) , .DATA_R0 ( data_R0 ) , .DATA_G0 ( data_G0 ) , .DATA_B0 ( data_B0 ) , .DATA_R1 ( data_R1 ) , .DATA_G1 ( data_G1 ) , .DATA_B1 ( data_B1 ) , .ctrl_done ( enc_done ) ) ; image_write #( .INFILE ( `OUTPUTFILENAME ) ) u_image_write ( .HCLK(HCLK) , .HRESETn(HRESETn) , .hsync(hsync) , .DATA_WRITE_R0 ( data_R0 ) , .DATA_WRITE_G0 ( data_G0 ) , .DATA_WRITE_B0 ( data_B0 ) , .DATA_WRITE_R1 ( data_R1 ) , .DATA_WRITE_G1 ( data_G1 ) , .DATA_WRITE_B1 ( data_B1 ) , .Write_Done( ) ) ; //------------------------------------------------- // Test Vectors //------------------------------------------------- initial begin HCLK = 0 ; forever #10 HCLK = ~HCLK ; end initial begin HRESETn = 0 ; #25 HRESETn = 1 ; end endmodule |
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